1. Field of the Invention
The present invention relates to an analog-digital converter. More specifically, the present invention relates to a pipelined folding analog-digital converter.
2. Discussion of Related Art
The conventional analog-digital converter is composed of a first quantizer that quantizes an analog voltage, a residue circuit that outputs a value subtracting an output of the first quantizer from the analog voltage, and a second quantizer that quantizes an output of the residue circuit. The first quantizer can be called a coarse quantizer, and the second quantizer can be called a fine quantizer. A folding analog-digital converter replaces the residue circuit of the conventional analog-digital converter with a folder, thereby improving performance, especially speed, of the analog-digital converter. A pipelined folding analog-digital converter introduces a pipeline scheme into the analog-digital converter having a number of folders, thereby improving the performance of the folding analog-digital converter. A pipeline folding scheme was disclosed on February, 2002 by Myung-Jun Choe in ‘IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 2’ entitled to ‘An 8-b 100-MSample/s CMOS Pipelined Folding ADC’
FIG. 1 is a pipelined folding analog-digital converter according to the prior art. The pipelined folding analog-digital converter according to the prior art comprises a sample-and-hold unit 1, a reference voltage generator 2, a first folder 3, a first track-and-hold unit 4, a second folder 5, a second track-and-hold unit 6, first and second quantizers 7 and 8, a third folder 9 and a digital decoder 10.
The pipelined folding analog-digital converter according to the prior art processes a difference between an analog input voltage Vin and a reference voltage by amplifying it through the first and second folders 3 and 5, so that there exists a problem that resolution that can be implemented is limited due to mismatch of devices within the first and second folders 3 and 5. Further, to apply the pipeline scheme, it has the first and second track-and-holder units 4 and 6 between each stage. That is, it is a structure connecting a switch and a capacitor, which exist between each stage, in a parallel. Therefore, it should be designed such that the previous stage and the next stage have the same signal level, and when the signal level is not identical, signal linearity can be degraded. Further, there is a problem that it is difficult to decode lower bits when configuring multiple stages with a folder that has an odd number of folding factors.